library IEEE;
use IEEE.std_logic_1164.all;

entity loadablereg is
	port (d : in std_logic_vector(15 downto 0);
		q : out std_logic_vector(15 downto 0);
		en,clk,reset : in std_logic);
end loadablereg;

architecture dataflow of loadablereg is
begin
	process(clk,reset)
	begin
	if reset = '1' then
		q <= "0000000000000000"; -- or whatever you want
	elsif (clk'EVENT and clk = '1') then
		if en = '1' then
			q <= d;
		end if;
	end if;
	end process;
end dataflow;
